Design-Reuse

Synopsys Enhances DesignWare Synthesizable IP for AMBA 2 and AMBA 3 AXI Protocols

MOUNTAIN VIEW, Calif. -- April 25, 2007-- Synopsys, Inc. (Nasdaq: SNPS - News), a world leader in semiconductor design software, today announced the 2007.04a release of DesignWare® synthesizable ...
EDN

Self-timed interconnect solution supports AXI bus protocol

SAN FRANCISCO — EDA and intellectual property (IP) startup Silistix Ltd. has added support for the on-chip AMBA AXI bus protocol to the company's synthesized self-timed interconnect technology, ...
EDN

Bridging Xilinx Streaming Video Interface with the AXI4-Stream Protocol

The ARM® core AMBA® specification (version 4.0) AXI interconnect standard includes three Advanced eXtensible Interface version 4 (AXI4) interconnect protocols—AXI4 interconnect, AXI4-Lite protocol, ...
Design-Reuse

Synopsys Introduces the Industry's First Verification IPs for Arm AMBA 5 AXI-J and APB-E

Arm recently announced the availability of the next iteration of the Arm® AMBA® 5 AXI and APB – AXI Issue J (AXI-J) and APB issue E (APB-E). These new specifications introduce several exciting ...
Semiconductor Engineering

Introduction To AXI Protocol

When part of a team, your group can become more capable than a single individual, but only if your team can work together and communicate effectively. Having members of a group talk over each other ...
Semiconductor Engineering

Mixing Interface Protocols

Continuous and pervasive connectivity requires devices to support multiple interface protocols, but that is creating problems at multiple levels because each protocol is based on a different set of ...
Electronic Design

Formal Techniques for Protocol Verification: A Case Study On Verifying the ARM ACE Protocol

More processors on SoCs means more sophisticated cache control. This article describes formal techniques for verifying cache coherency for the ARM AMBA AXI Coherency Extensions (ACE) protocol. Fig 1.