Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
EDN

Aldec tools validated for Lattice devices

SAN FRANCISCO — Mixed-language simulation and EDA tool provider Aldec Inc. said Monday (May 15) that programmable logic supplier Lattice Semiconductor Corp. has validated Aldec's Riviera and ...
EDN

Partnership Provides Benefits of Third Party Tools to Proprietary Design Environment

QuickLogic Corporation and Aldec, Inc. announced that QuickLogic is integrating Aldec's Active-HDLTM Lite verification environment into its QuickWorks QuickLogic and Aldec have partnered to provide ...
Electronic Design

EDA Update: Mixed HDL/C-Language Design For FPGAs

Mixed HDL/C-Language design for FPGAs recently debuted, courtesy of Aldec Inc. and Celoxica Ltd. The Active-HDL+C integrated FPGA design environment combines Aldec's Active-HDL design entry and ...
Electronic Design

Graphical Code Coverage Tool Speeds Design Debugging

Code Snooper, a code coverage software tool for use with the Active-HDL design and verification environment is integrated with the Active-HDL simulation kernel and does not require additional ...