Open Core Protocol (OCP) [1][2] is a common standard for Intellectual Property (IP)core interfaces. OCP facilitates IP core plug-and-play and simplifies reuse by decoupling the cores from the on-chip ...

This document motivates the need for a cache-coherent multicore, symmetric multiprocessor (SMP) with applications to embedded control and audio processing. It describes the current state of the art in ...

Scaling processing performance beyond the frequency and power envelope of single core systems has led to the emergence of multi-core clusters. Data access management within such processing systems ...

MIPS32 1004K coherent processing system is a multithreaded, multiprocessor licensable IP multiprocessor platform that supports up to four single- or double-threaded processor cores connected together ...

Although snoopy virtual-bus approaches are the first step, hybrid snoopy-directory schemes will be the next trend in embedded coherence. Without a doubt, embedded systems-on-a-chip (SoCs) are becoming ...

The Cache Coherent Interconnect for Accelerators standard, or CCIX (pronounced “see 6”), is built on PCI Express (PCIe) to provide a chip-to-chip interconnect for high-speed hardware accelerators. It ...