EDN

Improve top-level simulation strategy for switching DC-DC converters

Just before fabrication, the design flow of all integrated circuits (ICs) culminates in transistor-based, top-level simulations. Unfortunately, verifying functionality, connectivity, and performance ...
EE World Online

How to spot and fix the hidden modeling gaps in analog simulation

This technical FAQ examines three modeling gaps identified in engineering literature and outlines algorithmic methods to address them.
Purdue University

Complete atom-by-atom transistor simulation run in 15 minutes

WEST LAFAYETTE, Ind. - A simulation of electrical current moving through a futuristic electronic transistor has been modeled atom-by-atom in less than 15 minutes by Purdue University researchers. The ...
EDN

Taking power analysis to the transistor level for a full chip

Almost every chip being taped out today is mixed-signal in nature. In addition to increased integration of analog and RF blocks, designers are using complex power-management techniques to minimize ...
it.tmcnet

Berkeley Design Announces Fractional-N PLL Transistor-Level Noise Analysis

Berkeley Design Automation has announced the closed-loop noise analysis of fractional-N phase-locked loops (PLLs) at the transistor level. The company is a provider of Precision Circuit Analysis ...
Business Wire

Magma Acquires ACAD, Introduces FineSim Pro Circuit Simulator; Full-Chip, Tri-Mode Circuit Simulator Enables Simulation of Entire Mixed-Signal SoCs at Transistor Level

SANTA CLARA, Calif.--(BUSINESS WIRE)--July 24, 2006--Magma(R) Design Automation Inc. (Nasdaq:LAVA), a provider of semiconductor design software, today announced the availability of FineSim(R) Pro, the ...
Design-Reuse

Mixed-Signal Verification Methodology Using Nanosim Integration with VCS

With gate counts and system complexity growing exponentially, new submicron technologies pose many challenges in both the design and verification domains. Nowadays, many high-performance ...
Semiconductor Engineering

Transistor-Level Performance Evaluation Based On Wafer-Level Process Modeling

Three years ago, I wrote a blog entitled “Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation,” in which I described the seamless connection between the SEMulator3D virtual ...
Design-Reuse

Cadence Introduces Voltus-Fi Custom Power Integrity Solution, Delivering Foundry-Certified SPICE-Level Accuracy for Transistor-Level Power Signoff

SAN JOSE, Calif. -- Aug 4, 2014 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today introduced Cadence® Voltus™-Fi Custom Power Integrity Solution, a ...
Semiconductor Engineering

Transistor-Level Verification Returns

Technologies that had become specialist tools are moving back into mainstream usage; shift left is not just about doing things earlier in the flow. A few decades ago, all designers did ...
WJFW

Innatera Selects Synopsys Simulation to Scale Brain-Inspired Processors for Edge Devices

Innatera adopts Synopsys simulation technology to help design neuromorphic chips that enable low-power AI for wearables, ...