GitHub

ORTiS Solver C++ Code Generation Tools for Real-Time Simulation of Power Electronic Systems

Code generation tools for creation of CPU or FPGA real-time simulation C++ solvers of nonlinear electrical and power electronic systems. These tools are part of the Open Real-Time Simulation (ORTiS) ...
IEEE

Use of HDL code checkers to support the IP entrance check - a requirement analysis

Abstract: Systems for coding style analysis, so called hardware description languages (HDL) code checkers, can accomplish an important contribution for the IP entrance check, that means selection, ...
IEEE

Accelerating video and image processing design for FPGA using HDL coder and simulink

Abstract: Video and Image Processing solution requiring high throughput rate are often implemented in a dedicated hardware such as FPGA. The design process traditionally uses Verilog and VHDL for ...
GitHub

HDL Tutorial images are updated

Examples/AIENGINE_plus_PL/AIE_HLS/AIE_HLS_with_interface/aie_hls.slx aie_hls.slx images Examples/AIENGINE_plus_PL/AIE_HLS/AIE_HLS_with_interface/images/screen_shot ...
archive

Filter Design HDL Coder User`s Guide

Due to a planned power outage on Friday, 1/14, between 8am-1pm PST, some services may be impacted. A line drawing of the Internet Archive headquarters building façade. An illustration of a magnifying ...
EDN

Automating rule sets for safety-critical HDL coding

During the development process for safety-critical designs, all precautions should be taken to prevent device failures from all foreseeable sources, including those due to poor design methods and ...